Conventionally, in the design of digital circuits, particularly application-specific integrated circuits (ASIC), standard cells are often pre-designed and saved in cell libraries. At the time integrated circuits (applications) are designed, the standard cells are retrieved from the cell libraries, and placed to desirable locations. Routing is then performed to connect the standard cells with each other, and with other customized circuits on the same chip.
With the advancement of integrated manufacturing processes, design-for-manufacturing (DFM) effects become more significant. For example, the length of diffusion (LOD) significantly affects the performance of the integrated circuits. However, existing ASIC design methods do not adequately take the DFM effects into account. Currently, the DFM effects are not considered during placement and route stages at all. After the placement and route stages are finished, the analysis of the resulting circuit may involve the consideration of some DFM effects. However, at this stage, it is too late to change the circuit to take full advantage of the DFM effects.